Intel’s exploration and layout in the field of cutting-edge technology hold industry benchmark significance, with its published technology roadmaps and achievements providing an important reference direction for the semiconductor industry. At the IEDM 2024 conference, Intel unveiled seven technical papers, showcasing innovative advancements in multiple key areas. These technologies span from FinFET to 2.
5D and 3D packaging (EMIB, Foveros, Foveros Direct), the PowerVia backside power delivery technology that will be applied in Intel’s 18A node, as well as the all-around gate (GAA) transistor RibbonFET. Additionally, Intel revealed several advanced packaging technologies aimed at the future, offering a new perspective for driving industry development. Among these frontier technologies, three core areas are particularly noteworthy: advanced packaging for AI development, transistor scaling technology, and interconnect scaling technology. At the IEDM 2024 conference, Sanjay Natarajan, Senior Vice President of Intel Foundry and General Manager of Technology Research, detailed the key breakthroughs in these areas. Breakthroughs in Advanced Packaging: Selective Layer Transfer Technology heterogeneous integration has become the mainstream means of achieving performance enhancement in today’s chip industry. However, heterogeneous integration technology faces significant challenges. Current heterogeneous integration technology primarily uses “wafer-to-wafer bonding” (Wafer-to-Wafer HB) or “chip-to-wafer bonding” (Chip-to-Wafer HB), which can limit throughput, chip size, and thickness due to sequential assembly of chiplets. Intel has broken through the current technological bottleneck of heterogeneous integration with Selective Layer Transfer technology. This technology can efficiently complete the parallel transfer of over 15,000 chiplets with ultra-high efficiency, achieving an improvement over traditional methods that can take hours or days in just a few minutes. Its innovative sub-micrometer chiplet transfer supports chiplets that are only 1 square millimeter in size and have a thickness of 1/17th of a human hair. This provides a flexible and cost-effective heterogeneous integration architecture, making the hybridization of processor and memory technologies possible. Intel Foundry has taken the lead with inorganic infrared laser debonding technology, achieving a technological breakthrough in chiplet transfer, and promoting the development of advanced heterogeneous integration technology required for flagship AI product development. Sanjay Natarajan, Senior Vice President of Intel Foundry and General Manager of Technology Research, stated: “We have reason to expect that this technology will become as popular in the industry as the PowerVia backside power delivery technology.”We are actively pioneering and promoting the development of this technology, and I believe we will see leading companies in the industry gradually adopting it.” In the era of AI, Intel has proposed a comprehensive packaging solution to achieve the mass production of AI systems. In addition to selective layer transfer technology, Intel is also focusing on:
Advanced Memory Integration: Addressing capacity, bandwidth, and latency bottlenecks to enhance performance. Hybrid Bonding Interconnect Scaling: Achieving high-efficiency and high-bandwidth-density connections between heterogeneous components. Modular System Expansion: Reducing network latency and bandwidth limitations through connectivity solutions. Breakthroughs in GAA Transistors: The advancement of physical and two-dimensional material transistor technology has always been one of Intel’s main businesses, with the goal of achieving one trillion transistors by 2030. Intel has demonstrated technological breakthroughs in Gate-All-Around (GAA) RibbonFET transistors, successfully reducing the gate length to 6nm and achieving a silicon channel thickness of 1.7nm. Through precise engineering design of the silicon channel thickness and source-drain junctions, leakage current and device degradation are effectively reduced, enhancing the performance stability of transistors at extremely short gate lengths. Intel research data shows that compared to other advanced node technologies, RibbonFET has higher electron mobility and better energy efficiency characteristics at a 6nm gate length. In addition, RibbonFET achieves the best subthreshold swing (SS) and drain current suppression performance (DIBL). The left image is a transmission electron microscope (TEM) image, the middle displays some key parameters of these transistors, and the right image is a graph of gate length and electron velocity. This progress demonstrates industry-leading levels in optimizing short-channel effects, laying the foundation for future higher-density, lower-power chip designs, while promoting the continuous development of Moore’s Law and meeting the stringent semiconductor performance requirements for the next generation of computing and AI applications. To advance the development of GAA transistor technology, Intel is also focusing on two-dimensional semiconductor materials. According to Sanjay Natarajan, specifically, Intel has introduced two-dimensional (2D) NMOS and PMOS transistors in GAA technology, with 2D MoS2 as the channel material, combined with high-k HfO2 as the gate oxide layer, achieving precise control through ALD (atomic layer deposition) process.The cross-sectional imaging below clearly shows the structural integration among gate metal, HfO₂ oxide and two-dimensional MoS2. Its overall thickness is at the nanometer level. The drain-source spacing (L_SD) is less than 50nm. The subthreshold swing (SS) is lower than 75mV/d. The maximum current performance (I_max) reaches above 900µA/µm, which can significantly enhance the gate’s control ability over the channel.
The chart on the right compares Intel’s research results (THIS WORK) with other similar studies, showing obvious advantages in driving current and subthreshold swing. Intel’s research verifies that combining GAA architecture and 2D materials, the transistor performance is a leap. And once Intel pushes the performance of silicon-based channels to the limit, GAA transistors using 2D materials are likely to become a reasonable direction for the next step of development. As observed by Intel, the exponential growth trend of transistor numbers conforms to Moore’s Law. From microcomputers to data centers, the number of transistors doubles every two years. However, with the continuous increase of AI workloads, AI-related energy consumption may exceed the current total power demand of the United States in 2035. The energy bottleneck becomes a key challenge for future computing development. Therefore, what is needed in the future are new transistors. The next-generation transistors need to have an ultra-steep subthreshold swing (lower than 60mV/dec) and extremely low static leakage current (I_off), and support operation at ultra-low supply voltages (<300mV). Intel is also continuously exploring at the material and physical levels and has demonstrated transistors with Ge (germanium) nanoribbon structures at IEDM. Its 9nm thickness and innovative design combined with oxide interfaces lay the foundation for achieving low power consumption and efficient transmission. Intel further studies the combination of high-k dielectric materials and new interface engineering to develop more energy-efficient and efficient next-generation transistors. Intel also calls on the entire industry to jointly promote the revolution of transistor technology to meet the needs of AI applications in the era of trillions of transistors. By summarizing the development of transistors in the past 60 years, Intel also proposes development goals for the next 10 years: 1) Transistors that can work at ultra-low supply voltages (<300mV) must be developed to significantly improve energy efficiency and provide support for universal AI applications. 2) The technology of continuously increasing the number of transistors is feasible, but the revolutionary breakthrough in energy efficiency will be the focus of future development. Breakthrough in interconnect scaling: Ruthenium lines. As transistors and packaging technologies continue to shrink, interconnects have become the third key element in the semiconductor system.These interconnecting wires are responsible for connecting trillions of transistors. However, we can clearly see that the era of copper interconnects is gradually coming to an end. There is a practical problem with copper interconnects: barrier layers and seed layers need to be added during use. As the size continues to shrink, these relatively high-resistance layers occupy more available space. Intel has observed that when the line width continues to shrink, the resistivity of copper wires rises exponentially to an unacceptable level.
Therefore, although transistor sizes are getting smaller and smaller, and density and performance are continuously improving, traditional wiring methods can no longer meet the need to connect all transistors. Intel’s breakthrough lies in the adoption of cost-effective air-gap ruthenium (Ru) lines as a potential alternative to copper interconnects. This air-gap solution does not require expensive lithography technology or self-aligned via processes. It cleverly combines air gaps, subtractive ruthenium processes, and patterning, and is expected to create a reasonable next-generation interconnect technology to match future transistor and packaging technologies. This new process achieves a capacitance reduction of up to 25% under matching resistance conditions at a pitch of less than 25nm, effectively improving signal transmission speed and reducing power consumption. High-resolution microscopic imaging shows the precise alignment of ruthenium interconnects and vias, verifying that there are no via breakthroughs or serious misalignments. The subtractive ruthenium process supports high-volume manufacturing (HVM) and has economic and reliable practical applications by eliminating complex air-gap exclusion zones and selective etching requirements. In the end, the semiconductor industry is a highly complex ecosystem that requires joint efforts from all parties to achieve breakthroughs. Intel’s innovative achievements in fields such as packaging, transistors, and interconnects provide valuable experience and inspiration for the entire industry. As Sanjay Natarajan said, Intel’s goal is to provide a roadmap for the entire industry to coordinate and unify all our research and development funds and efforts. In this way, next-generation products and services can drive the entire industry forward and continue to advance Moore’s Law. Intel indeed always sees itself as the guardian of Moore’s Law and is committed to shouldering this responsibility and continuously exploring new technologies to advance Moore’s Law. This is not only for Intel’s interests, but also for the common interests of the entire industry.
