At IEDM2024, Intel Foundry’s technical research team demonstrated pioneering advancements in transistor and packaging technology, which can help meet future AI computing power demands. At IEDM 2024 (2024 IEEE International Electron Devices Meeting), Intel Foundry showcased multiple technological breakthroughs that can drive the semiconductor industry’s development over the next decade and beyond. Specifically, in terms of new materials, the subtractive Ruthenium interconnect technology can reduce interline capacitance by up to 25%①, which helps improve chip-level interconnectivity.
Intel Foundry also pioneered a heterogeneous integration solution for advanced packaging, capable of enhancing throughput by up to 100 times②, enabling ultra-fast chip-to-chip assembly. Furthermore, to further advance the miniaturization of the gate-all-around (GAA) transistor, Intel Foundry demonstrated the silicon-based RibbionFET CMOS (Complementary Metal-Oxide-Semiconductor) technology, as well as the gate oxide module for 2D FETs (2D Field-Effect Transistors) used in miniaturization, to improve device performance. As the industry moves towards the goal of achieving one trillion transistors on a single chip by 2030, breakthroughs in transistor and interconnect miniaturization technologies, along with future advanced packaging capabilities, are becoming increasingly critical to meet the growing demand for more energy-efficient, high-performance, and cost-effective computing applications, such as AI. We also need to explore new materials to enhance the role of Intel Foundry’s PowerVia backside power delivery technology in alleviating interconnect bottlenecks and further miniaturizing transistors. This is essential for continuing to advance Moore’s Law and driving semiconductor innovation for the AI era. ① Technical paper ‘Subtractive Ruthenium Interconnect Technology with Air Gap’, authors: Ananya Dutta, Askhit Peer, Christopher Jezewski ② Technical paper ‘Selective Layer Transfer: Industry-Leading Heterogeneous Integration Technology’ (authors: Adel Elsherbini, Tushar Talukdar, Thomas Sounart) Intel Foundry has explored several paths to address the foreseeable interconnect miniaturization limitations when developing future process nodes using copper materials, improve existing packaging technologies, and continue to define and plan the transistor roadmap for GAA and other related technologies: – Subtractive Ruthenium Interconnect Technology: To enhance chip performance and improve interconnectivity, Intel Foundry demonstrated the subtractive Ruthenium interconnect technology.By adopting ruthenium, a new, crucial, and alternative metallization material, and utilizing thin film resistivity and airgap, significant progress has been made in interconnect miniaturization. Intel Foundry has taken the lead in demonstrating a feasible, mass-producible, and cost-effective subtractive ruthenium interconnect technology on research and development test equipment. [Technical paper ‘Subtractive Ruthenium Interconnect Technology Utilizing Airgap’, by Ananya Dutta, Askhit Peer, Christopher Jezewski].
This process introduces airgap and eliminates the need for expensive lithographic airgap exclusion zones around vias. It can also avoid the use of self-aligned vias with selective etching. When the pitch is less than or equal to 25 nanometers, the airgap achieved by subtractive ruthenium interconnect technology reduces the interline capacitance by up to 25%. This indicates the advantage of subtractive ruthenium interconnect technology as a metallization scheme to replace copper damascene processes in closely spaced layers. This solution is expected to be applied in Intel Foundry’s future process nodes. Selective Layer Transfer (SLT): To increase throughput by up to 100 times in chip packaging and achieve ultra-fast inter-chip packaging, Intel Foundry has demonstrated the Selective Layer Transfer technology for the first time. This is a heterogeneous integration solution that can integrate ultra-thin dies with higher flexibility. Compared with traditional chip-to-wafer bonding technology, Selective Layer Transfer allows chips to be smaller in size and have a higher aspect ratio. This technology also brings higher functional density and can be combined with hybrid bonding or fusion bonding processes to provide a more flexible and cost-effective solution for packaging dies from different wafers. This solution provides a more efficient and flexible architecture for AI applications. Silicon-based RibbonFET CMOS transistor: To push the miniaturization of RibbonFET GAA transistors to a higher level, Intel Foundry has demonstrated a silicon-based RibbonFET CMOS transistor with a gate length of 6 nanometers. While significantly shortening the gate length and reducing the channel thickness, it has reached the industry-leading level in suppressing short-channel effects and performance.This breakthrough paves the way for one of the key cornerstones of Moore’s Law—the continuous reduction of gate length.
Gating oxide layer for 2D GAA transistors: To further accelerate GAA technology innovation beyond CFET (Complementary Field-Effect Transistor), Intel Foundry has demonstrated its research in the manufacturing of 2D GAA NMOS (N-type Metal-Oxide-Semiconductor) and PMOS (P-type Metal-Oxide-Semiconductor) transistors, focusing on the development of the gate oxide layer module, which has shrunk the transistor gate length to 30 nanometers. The research also reports on the industry’s progress in the field of 2D TMD (Transition Metal Dichalcogenides) semiconductors, which are expected to become alternatives to silicon in advanced transistor processes in the future.
In terms of 300mm GaN (Gallium Nitride) technology, Intel Foundry is also continuing its pioneering research. GaN is an emerging material for power and RF (Radio Frequency) devices, offering stronger performance and the ability to withstand higher voltages and temperatures compared to silicon. On the 300mm GaN-on-TRSOI (Silicon on Trapped-Surface Oxide-Layer Insulator) substrate, Intel Foundry has manufactured the industry-leading high-performance scaled-enhanced GaN MOSHEMT (Metal-Oxide-Semiconductor High-Electron-Mobility Transistor). Advanced processes such as GaN-on-TRSOI substrates can bring stronger performance for power and RF devices, reducing signal loss, improving signal linearity, and enabling advanced integration solutions based on substrate backside processing.
Additionally, at IEDM 2024, Intel Foundry shared its vision for the future development of advanced packaging and transistor shrinkage technologies to meet the needs of various applications, including AI. The following three key innovation focuses will help AI develop towards higher energy efficiency in the next decade:
– Advanced memory integration to eliminate bottlenecks in capacity, bandwidth, and latency;
– Hybrid bonding for optimizing interconnect bandwidth;
– Modular systems and corresponding connection solutions.
Intel Foundry also issued a call to action to develop critical and breakthrough innovations, continuously advancing transistor shrinkage and driving the realization of the ‘trillion-transistor era’. Intel Foundry outlined how the development of transistors that can operate at ultra-low voltages (below 300 millivolts) will help address the increasingly severe thermal bottlenecks and significantly improve power consumption and heat dissipation.
